A case study on the Smart MCU board (STM32F): 210 of 210 connections routed, 100% complete, DRC-clean.
The board is open source: github.com/juliengouban/STM32F-board
Open the Smart MCU board project in DeepPCB.
A dense digital board built around a QFN microcontroller is a routing grind: dozens of GPIO nets fanning out from a single package to connectors on every edge, a USB pair that has to stay matched, a debug port, two crystals, and a power path that has to reach every pin cleanly. The Smart MCU board packs 88 components and 146 unrouted airwires into a compact 4-layer outline.
This tutorial uses the Smart MCU board, an open-source STM32F design, as a real-world case study. We walk through the full DeepPCB workflow: reading the board, pouring the inner planes, setting the constraints, and running the cloud router to a finished, DRC-clean result, including one moment where Cooper is honest about a number it cannot compute.
As imported: 146 unrouted airwires, nothing routed yet.
The Result at a Glance
One automated pass on the Smart MCU board, with the constraints set up first (revision 45):
| Metric | Result |
|---|---|
| Routing completion | 100% (210 of 210 airwire connections, 0 unrouted) |
| Vias placed | 42 (mostly power and ground vias to the inner planes, not signal-layer vias) |
| Total track length | 1182.90 mm |
| Routing time | 18 minutes 8 seconds |
| Differential pairs | 1 of 1 routed |
| Design rule check | Clean (one minor board-setup anomaly) |
The Automation Profile
The whole setup and route was driven from the Cooper chat. Cooper read the board, proposed the fixes it saw, and executed the approved actions:
- pour a GND plane on inner layer 1 and a +3.3V plane on inner layer 2
- set both inner layers to POWER type
- create a power net class (+3.3V, +9V) at a wider 20 mil track
- create the USB differential pair (PA11 / PA12) at a 0.15 mm gap
- protect all existing wires and vias
- route
Hardware Architecture
Before touching a trace, you read the circuit. The Smart MCU board (88 components, 43 nets) breaks into four functional blocks.
- Power path: power enters on a +9V input and an LDO regulator (U1) drops it to a +3.3V logic rail, with bulk and bypass capacitors on both rails.
- Microcontroller: an STM32F QFN (U2) runs the board, with GPIO fanning out to the edge connectors, a SWD debug port (SWCLK / SWDIO), and the reset line (NRST).
- USB: the STM32 USB data lines sit on PA11 (D-) and PA12 (D+), which is why they are treated as a differential pair.
- Clocks: a main crystal and a 32 kHz RTC crystal (Y1 / Y2) provide the system and real-time clocks.
Layer Stackup
The board is a 4-layer stack. The two inner layers become the reference and power planes; the top and bottom carry the signals (with local pours):
| Layer | Type | Assignment |
|---|---|---|
| Top Layer | Signal | Component pads, high-speed traces, local +3.3V / GND pours |
| GND_layer (inner 1) | Power | Solid GND reference plane |
| 3.3V_layer (inner 2) | Power | Solid +3.3V power plane |
| Bottom Layer | Signal | Low-speed routing, local GND pour |
Assigning GND and +3.3V to the two inner planes gives every signal a short vertical path to power and ground, which is what keeps the top and bottom layers clean.
The DeepPCB Routing Workflow
Cloud neural routers like DeepPCB can collapse hours of routing into minutes, but only when the board is set up correctly first. This run followed a short sequence.
Step 1: Pour the inner planes
First we flood the inner layers: a GND pour on inner layer 1 and a +3.3V pour on inner layer 2, and set both layers to POWER type. With solid planes in place, every ground and power pin drops straight to a via instead of routing across the surface.
Step 2: Set the net classes
The power nets (+3.3V and +9V) get their own class with a wider 20 mil track, so the higher-current rails carry more copper than the default signal width.
Step 3: Define the USB differential pair
The STM32 USB data lines on PA11 (D-) and PA12 (D+) are set up as a differential pair with a 0.15 mm gap, so the router keeps them matched and routed together.
Step 4: Honest about what it cannot compute
Asked for the exact differential impedance of that pair, Cooper does not guess. This board file carries no stackup data (dielectric thickness, material, layer separation), which is what a real impedance calculation needs, so Cooper says so plainly and lists what you would need rather than inventing a number. That honesty is the point: a tool you can trust tells you where its inputs run out.
Step 5: Protect the existing work
Before the solver runs, we protect all existing wires and vias, locking their paths so the router builds the remaining connections around them instead of moving or deleting them.
Step 6: Route
With the constraints in place, the router runs and resolves the open airwires. It routed the 146 open connections to bring the board to 210 of 210 complete: 100% routed, 42 vias, 1182.90 mm of track, in 18 minutes 8 seconds, with all 6 differential pairs routed (see the scorecard at the top).
The decoupling network
The router also respected the board’s decoupling rules. Every decoupling capacitor keeps a short, direct connection to its microcontroller power pin and a via straight down to the plane, rather than a long detour across the board.
The Routing, Layer by Layer
With the planes hidden, the routing on each signal layer is easy to read. Most of the work is on the top layer; the bottom stays sparse because the inner planes carry power and the return paths.
The Cooper Advantage
On this board we entered the setup step by step to show the workflow. Cooper does it for you. The moment a board lands, it reads the design, catches what is missing, and presents the fixes as clickable actions you approve or reject. Nothing changes without your say-so.
- Plane and power setup: it spots that the inner layers were typed as signal with no copper, and offers to pour GND and +3.3V and set them to power, so the board gets real reference and power planes before routing.
- Constraint capture: it flags the USB pins as a differential pair and gives the power rails a wider class, the setup work that usually eats the most time, in a few clicks.
- Honest by default: when a real answer needs data the board does not carry, it says so instead of guessing. That is what makes the automated numbers worth trusting.
The payoff is a board that is both connected and correctly set up before the router runs. That is what turns an automated pass into a result you can actually build.