STRF: RF Mixed-Signal board

FROM RATSNEST TO ROUTED: A case study on the STRF transceiver board (STM32L432 + nRF24L01P): 100% routed, DRC-clean, and ready for a first-pass build.

The board is open source: github.com/pms67/STRF-Kicad. You can explore the STRF board routing experiment in DeepPCB. 

Designing a compact, mixed-signal board that carries both a 2.4 GHz RF transceiver and a high-speed digital microcontroller is one of the harder layout jobs in electronics. You have to distribute power cleanly, keep digital switching noise out of a sensitive analog front end, and hold tight controlled-impedance targets on the high-speed lines, all in a footprint barely larger than a coin.

This tutorial uses the STRF Development Board (designed by Philip Salmony) as a real-world case study. We walk through the full DeepPCB workflow: reading the board, calibrating its 4-layer stackup, correcting the constraints, and running the DeepPCB to a finished, DRC-clean result.

The Result at a Glance

One automated pass on the STRF board, with the constraint corrections described below applied first:

Metric	Result
Routing completion	100% (98 of 98 airwires routed, 0 pins unrouted)
Vias placed	68
Routing time	Under 3 minutes (one automated pass)
Typical manual effort	2 to 3 hours for an experienced engineer
Design rule check	Clean by default
Build readiness	The routed design is electrically sound for a build at this size; full SI or EM simulation is not required at this scale

The Automation Profile 

The entire layout pass was driven by a short, explicit set of instructions passed to Cooper:

1. add GND plane on inner 1 and +3V3 on inner 2
2. update diff pairs to match the needed impedance based on physical stackup
3. remove C18 and C17 from decap rules
4. make C3 decap to component J3 pin 10
5. create net class: SPI bus nets use a smaller via (400:200 µm)
6. protect current routing
7. route for 10 min

Hardware Architecture and Schematic Breakdown

Before touching a single trace, you have to understand the circuit. The STRF board breaks into four functional blocks.

1. Power distribution and protection

• USB input: power enters through a USB Micro-B connector (J1).
• Overcurrent protection: a 100 mA fuse (F1) guards against downstream shorts.
• High-frequency filtering: a ferrite bead (FB1, 100 Ω at 100 MHz) blocks switching noise from feeding back into the USB host.
• Bulk decoupling: a 10 µF capacitor (C1) provides input reservoir capacitance. Host-side capacitance is kept at or below 10 µF to stay inside the USB inrush-current spec.
• LDO regulator: an XC6206P332MR (U1) drops the filtered +5V to a stable +3V3 rail at up to 200 mA.

2. Microcontroller core

• MCU: an STM32L432KBU6 (U3) in a QFN-32 package runs the board.
• USB interface: wired to the MCU internal USB peripheral. The MCU has on-die series resistors for the USB data lines (USB_D+ / USB_D-), so no external termination is needed.
• ESD protection: a USBLC6-2SC6 (U2) low-capacitance diode array sits next to the USB connector to clamp static discharge before it reaches the MCU.

3. nRF24L01P transceiver and RF front end

• RF IC: the nRF24L01P (U4) handles 2.4 GHz wireless, talking to the MCU over a medium-speed SPI3 bus.
• Reference clock: a 16 MHz crystal (Y1) with matched 12 pF load capacitors (C13, C14) sets the carrier accuracy.
• Matching network (balun): inductors (L1, L2, L3) and capacitors (C15, C16, C17, C18) convert the differential output on the nRF24L01P ANT1/ANT2 pins into a single-ended 50 Ω signal routed to the edge-mount SMA connector (J2). Note that C17 and C18 belong to this RF network, not to digital decoupling, which matters in Step 3.

PCB Topology and Layer Stackup

For mixed-signal and RF work, a 4-layer stackup is the baseline. A 2-layer board forces signal traces to share copper with broken ground, creating large return-current loops that radiate EMI and wreck RF performance.

The board uses a standard 1.6 mm 4-layer stackup:

Layer	Name	Type	Physical	Purpose
Layer 1	F.Cu (Top)	Signal	0.035 mm copper	Component footprints, RF matching network, high-speed differential pairs
Dielectric 1	core	FR4, εr = 4.5	0.48 mm	Primary isolation between top signals and ground
Layer 2	In1.Cu (Inner 1)	GND plane	0.035 mm copper	Solid ground reference and unbroken return path for Layer 1
Dielectric 2	prepreg	FR4, εr = 4.5	0.48 mm	Isolation core separating the two planes
Layer 3	In2.Cu (Inner 2)	+3V3 plane	0.035 mm copper	Dedicated power plane feeding clean +3V3 to the decoupling vias
Dielectric 3	core	FR4, εr = 4.5	0.48 mm	Isolation between bottom signals and the power plane
Layer 4	B.Cu (Bottom)	Signal	0.035 mm copper	Low-speed control logic, test points, auxiliary connections

The two inner layers do the heavy lifting. Layer 2 is a solid GND plane that gives every signal on Layer 1 an unbroken return path. Layer 3 is a dedicated +3V3 plane that delivers clean power straight to the decoupling vias.

Controlled-Impedance Modeling

USB data lines (90 Ω differential target)

The USB 2.0 data lines (USB_D+/USB_D- and USB_CONN_D+/USB_CONN_D-) run as edge-coupled microstrips on the outer layers. Their differential impedance comes from the trace geometry and the coupling between the two traces.

The tool starting template gave these pairs a loose profile (200 µm width, 250 µm gap). Checked against the real stackup, that gap is too wide and pushes the differential impedance well above the 90 Ω USB target, which causes reflections at the receiver. The router holds the track width and tightens the gap to land on target.

Differential parameter	Default	DeepPCB update
Track width (W)	200 µm (0.20 mm)	200 µm (0.20 mm), unchanged
Trace gap (S)	250 µm (0.25 mm)	150 µm (0.15 mm)
Resulting Zdiff	About 100 to 110 Ω (off target)	About 90 Ω (matched)

These are calculated estimates from the stackup parameters. For a production build, confirm them against your fabricator impedance calculator, since plating and prepreg compression can shift the result by a few ohms.

⚠ Keep USB pairs on the outer layers

DeepPCB keeps the USB pairs on F.Cu or B.Cu. If a USB trace dropped to an inner layer it would reference a different dielectric spacing, shift the impedance, and break the 90 Ω match.

The DeepPCB Routing Workflow

DeepPCB can collapse hours of routing into minutes, but only if the boundary constraints are right before the solver starts. The run above followed five phases.

1. Assign the inner planes: GND on Inner 1, +3V3 on Inner 2.
2. Calibrate the netclasses: tighten the USB diff-pair gap to 0.15 mm, and give the SPI bus its own class with a smaller 0.4 mm / 0.2 mm via.
3. Review the decoupling rules: drop the RF caps (C17, C18) from the decoupling cap pool, and add C3 as the decoupling cap for the NRST line (J3 pin 10).
4. Protect the existing routing so the solver leaves the hand-routed RF front end alone.
5. Run the router for 10 minutes.

Step 1: Establish the plane geometry

First we flood the inner layers. Inner Layer 1 becomes a copper pour tied to GND, and Inner Layer 2 becomes a pour tied to +3V3. The benefit are the following

1. Unbroken GND Plane: Localizes return currents directly beneath high-speed traces, shrinking loop areas to eliminate EMI and crosstalk.
2. Low-Impedance Power Plane: Minimizes rail resistance, preventing voltage drops and supply sag when your transceiver spikes its power amplifier.
3. Embedded Shielding & Decoupling: Creates a high-frequency, board-wide embedded capacitor that absorbs switching noise and shields sensitive analog circuits.

Step 2: Set the impedance and bus netclasses

The router reads the stackup and corrects the USB differential pairs, holding the 0.20 mm track and tightening the gap to 0.15 mm to hit the 90 Ω target (see the table above).

It also gives the SPI bus (SPI3_SCK, SPI3_MOSI, SPI3_MISO, SPI3_!CS) its own netclass. Instead of the default 0.8 mm drill / 0.4 mm annular via, the SPI class uses a smaller 0.4 mm drill / 0.2 mm annular via, the same compact via as the high-speed class, to keep routing channels open around the dense QFN pin field.

Step 3: Review the decoupling rules

Decoupling rules tell the router how tightly a capacitor must sit to its target pin. DeepPCB extracts them from the schematic automatically, but you review them and override where the automatic call is wrong. Two corrections here:

• RF caps removed from the decoupling cap pool: C17 and C18 are part of the RF matching network (Block 3), not digital decoupling for the transceiver rails. They are stripped from the decoupling constraints so the router does not force them next to a power pin.
• Reset line added: the microcontroller reset line had no decoupling cap rule. We add C3 as the direct decoupling cap for J3 pin 10 (the NRST net), keeping noise off the reset line so the MCU does not reset unexpectedly.

Step 4: Protect the hand-routed work

Before the solver runs, we flag the RF front end, the crystal, and the matching microstrips as protected. That locks their coordinates and trace paths, so the router builds the digital nets around them and never drops a via into the 50 Ω antenna line.

Step 5: Run the router

With the constraints locked, the engine runs for a fixed 10-minute budget and resolves the remaining airwires across the top and bottom layers. On this board it finished fast: all 98 airwires routed with 68 vias in under three minutes. The full breakdown is in the scorecard at the top of this article.

The Cooper Advantage

On this board we entered the corrections by hand to show each step. Cooper does this for you. The moment a board lands, it reviews the setup, catches the same issues, and presents them as clickable fixes you approve or reject. Nothing changes without your say-so.

• Impedance calibration: Cooper translates your stackup into real layout rules, tightening the USB pair gap to 0.15 mm to land a reflection-free 90 Ω match instead of leaving the pairs on a loose default.
• Plane allocation: it defines the inner planes up front. A solid GND pour on Inner Layer 1 gives every signal a clean return path and suppresses EMI, and a dedicated +3V3 plane on Inner Layer 2 holds the rail steady under RF transmit spikes.
• Circuit-aware decoupling: instead of treating the schematic as a black box, it separates the RF matching caps (C17, C18) from the digital decoupling pool and ties C3 directly to the NRST pin to protect the MCU from spurious resets.

The payoff is a layout that is both connected and correct before the router spins up. That is what turns an automated pass into a board you can actually build, and what prevents the silent respin a connect-the-dots autorouter would have handed you.