24 V ECU: 4-Layer Control Board

620 of 622 connections complete in 55 min 43 s, around the designer’s seven differential pairs.

Open the routed board in DeepPCB: https://app.deeppcb.ai/shared/xhMRck-mkkaRhRtBd9JXhA84oJkjrSxc3C0UJPSxtFw

This is the largest of the three boards Zach Peterson’s community sent us for our episode of Altium’s OnTrack podcast. It’s a 4-layer control board with two microcontrollers, a 24 V input, three CAN buses and four USB pairs. That comes to 139 nets and 622 connections.

The board isn’t ours, so we’re not sharing the design file. The link above opens our routed result.

The result at a glance

Routed in July 2026 by our engineer, on the board as submitted apart from the changes listed below.

The run kept going after revision 45, and the route kept improving. By revision 61 it still had 620 connected, with vias down from 228 to 226 and the track cut from 4,771.91 mm to 4,722.00 mm.

What we changed before the run

• We kept the seven differential pairs, four USB and three CAN, which the designer routed by hand, and asked Cooper to protect them. We deleted the rest of the designer’s tracks and all but 34 of the vias. The copper pours and inner-layer planes stayed in place.
• DeepPCB takes a single preferred width from Altium’s width rule. This board’s was 0.762 mm, too wide for its dense areas, so we set it to 0.254 mm. We also cut the default via from a 1.27 mm pad with a 0.711 mm hole to a 0.5 mm pad with a 0.25 mm hole.

What Cooper set up

Cooper read the board and proposed changes. It applied these:

• The two inner layers, GND and VCC, already carried copper but were typed as signal. Cooper set both to power.
• It created two wider classes: 0.3 mm for the 3.3 V and 5 V rails, and 0.5 mm for the 24 V rails and VBUS.

The 50 decoupling rules DeepPCB extracted when the board was imported needed no change.

We then asked it to let 24V_IN and 24V_OUT route on the VCC layer. Cooper first said no change was needed. We pointed out that they weren’t permitted to route on a power layer. Cooper agreed, explained that only nets with a plane on a power layer can route there, removed the two planes already on that layer, and rebuilt it as one split plane shared by +3V3, NetC61_1, 24V_IN and 24V_OUT. Then we started the route.

What we didn’t do

• We didn’t route the differential pairs. At the time of the run the router had no neck-down. The pairs are also drawn with arcs, which the import approximates because our arc support is still early. So we kept them as imported.
• Two connections are still open at revision 61. One is the last pin of a CAN pair, on a connector that is fixed in place. The router tried to complete it and gave up, and it was still open at the end of the run.
• Four capacitor pins sit outside the board outline in the file. The router leaves them out, which is why the count goes from 626 at import to 622.
• On import, DeepPCB set aside one clearance rule, DiffClearance, because it doesn’t read how that rule is scoped yet. The net-class clearance, 0.152 mm, applies instead.
• It isn’t a finished board. Our engineer estimates 8 hours of manual cleanup to finish it. The estimate for routing it by hand covers the whole board, including the parts the designer had already done.

See it on air

We showed this board in our episode of Altium’s OnTrack with Zach Peterson, from 32:11.

Watch: https://www.youtube.com/watch?v=apvE_ElRhiA&t=1931s

Listen: https://podcast.altium.com/e/ai-pcb-routing-without-the-epic-fails-inside-deeppcb/

More on the episode: https://deeppcb.ai/natural-language-pcb-routing/